`timescale 1ns / 1ps

module memory_game_top_sim();
    reg clk_i = 'b0;
    reg rst_i = 'b0;
    reg start0_i = 'b0;
    reg start1_i = 'b0;
    reg start2_i = 'b0;
    reg start3_i = 'b0;
    reg [7:0] sw_i = 'b0;
    wire [7:0] high_bus;
    wire [7:0] low_bus;
    wire [7:0] digit_en;
    
    memory_game_top UUT(
        clk_i,
        rst_i,
        start0_i,
        start1_i,
        start2_i,
        start3_i,
        sw_i,
    
        high_bus,
        low_bus,
        digit_en
	);
	
	reg [31:0] i;
	
	always #1 clk_i = ~clk_i;
	
	initial begin
	    #5 start0_i = 'b1;
	    #300 start0_i = 'b0; start1_i = 'b1;
	    #50 start1_i = 0; start2_i = 1;
	    for (i=0 ; i<5 ; i=i+1) begin
	        #20 sw_i = 8'b0000_0101;
	        #20 start3_i = 'b1;
	        #20 start3_i = 'b0;
	    end
	    $stop;
	end
endmodule
